Design of a Self-Timed VLSI Multicomputer Communication Controller,

Abstract

We describe the design of the network design frame, (NDF), a self-timed routing chip for a message-passing concurrent computer. The NDF uses a partitioned data path, low-voltage output drivers, and a distributed token-passing arbiter to provide a bandwidth of 450Mbits/sec into the network. Wormhole routing and bidirectional virtual channels are used to provide low latency communications, less than micro seconds latency to deliver a 216 bit message across the diameter of a 1K node machine. To support concurrent software systems, the NDF provides two logical networks, one for user messages and one for system messages, that share the same set of physical wires. To facilitate the development of network nodes, the NDF is a design frame. The NDF circuitry is integrated into the pad frame of a chip leaving the center of the chip uncommitted.

Open PDF

Document Details

Document Type
Technical Report
Publication Date
Nov 01, 1987
Accession Number
ADA194567

Entities

People

  • Bill Dally
  • Paul Song

Organizations

  • Massachusetts Institute of Technology

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Arbitration
  • Artificial Intelligence
  • Bandwidth
  • Communication Channels
  • Communication Networks
  • Computer Science
  • Computers
  • Crossbar Switches
  • Fabrication
  • Hypervelocity Flow
  • Logic
  • Low Voltage
  • Massachusetts
  • Networks
  • Shift Registers
  • Switches
  • Two Dimensional

Fields of Study

  • Computer science

Readers

  • Computer Networking
  • Integrated Circuit Design and Technology.
  • Parallel and Distributed Computing.