Fault-Tolerant Signal Processing Architectures with Distributed Error Control.
Abstract
Digital filtering architectures that simultaneously offer advantages for VLSI fabrication and contain distributed error-control are presented. Such structures require parallelism as well as inherent error-control capabilities because VLSI implementations are susceptible to temporary and intermittent hardware errors. Three different approaches have been developed to meet these requirements. The first method uses arithmetic decomposition to obtain highly parallel sections each operating with finite field arithmetic while the other two approaches concern finite and infinite convolutions over real or complex number arithmetic domains. Straightforward realizations depending on highly parallel algebraic decompositions were studied first. They involve the interconnection of fault-tolerant subsystems employing finite field arithmetic into which powerful cyclic error-correcting codes are imbedded naturally. The locations for fault-tolerance and the role of cyclic codes are detailed. Alternative realizations employing finite field transform domains and new techniques for protecting the transform coefficient are developed. These coefficients' special property, called the chord property, permits error detection and correction in the transform domain, and the proper selection of certain code parameters can enhance this capability. Fast transform algorithms with distributed error-control are possible because the interstage variables obey limited chord properties.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 01, 1985
- Accession Number
- ADA194599
Entities
People
- G. R. Redinbo
Organizations
- University of California