Processing-Enhanced SEU Tolerance in High Density SRAMs.

Abstract

We report theoretical calculations and experimental verification of an increase in memory cell SEU tolerance when Sandia's 2-micron-technology 16K SRAMs are fabricated with a radiation-hardened 1-micron CMOS process. An advanced two-dimensional transient transport-plus-circuit simulator has been employed to calculate the differential contributions from each of the vertical dimensional changes in the transition from the 2-micron process to the 1-micron process. Error cross-section data, performed at the Berkeley cyclotron on the first such device lot, indicate that total improvement in threshold LET is a factor of 2 or better. A saturation phenomenon associated with the high-LET events is described, and physical mechanisms responsible for the saturation are discussed. (RH)

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Document Details

Document Type
Technical Report
Publication Date
Jul 01, 1988
Accession Number
ADA195936

Entities

People

  • H. T. Weaver
  • J. S. Browning
  • J. S. Fu
  • K. H. Lee
  • Rokutano Koga

Organizations

  • The Aerospace Corporation

Tags

Communities of Interest

  • Advanced Electronics
  • Materials and Manufacturing Processes
  • Space

DTIC Thesaurus Topics

  • Air Force
  • Air Force Facilities
  • Capacitance
  • Classification
  • Corporations
  • Decoupling
  • Energy Transfer
  • Geometry
  • High Density
  • Resistance
  • Saturation
  • Security
  • Simulations
  • Simulators
  • Space Sciences
  • Thickness
  • Two Dimensional

Fields of Study

  • Physics

Readers

  • Integrated Circuit Design and Technology.
  • Nuclear and Radiation Engineering.
  • Solar Physics