Evaluation of Hardware Architectures for HF Antenna Arrays

Abstract

A variety of hardware architectures can be used for the implementation of HF adaptive signal processing algorithms. The purpose of this study is to evaluate various hardware structures, enumerate their advantages and disadvantages relative to the HF adaptive array problem, and to recommend the architectures best suited to the adaptive HF array systems. The hardware structures are compared based upon complexity which is determined by issues such as computational bounds, input requirements and characteristics of hardware structures. This evaluation is performed in a hierarchical manner. Application of general microprocessor technology is considered first. Integrated circuits tailored for digital signal processing applications is investigated next. Finally VLSI signal processing technology is considered. Included here are Systolic and Wavefront architectures.

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Document Details

Document Type
Technical Report
Publication Date
Jan 01, 1988
Accession Number
ADA196204

Entities

People

  • R. K. Balasubramaniam
  • Roger Spohn
  • Ryan Moates
  • Stephen Fechtel
  • Victor Frost

Organizations

  • University of Kansas

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Algorithms
  • Arithmetic
  • Bandwidth
  • Classification
  • Communication Systems
  • Computational Complexity
  • Computer Languages
  • Computer Programming
  • Computers
  • Data Transmission
  • Digital Signal Processing
  • Host Computers
  • Information Science
  • Language
  • Processing Equipment
  • Signal Processing
  • Two Dimensional

Fields of Study

  • Engineering

Readers

  • Phased Array Antenna Design.
  • Software Engineering.
  • Systems Analysis and Design