Transistor Sizing in the Design of High-Speed CMOS (Complementary-Symmetry Metal-Oxide-Semiconductor) Super Buffers

Abstract

An algorithm for sizing transistors for static Complementary-symmetry Metal-Oxide-Semiconductor (CMOS) integrated circuit logic design using silicon gate enhancement mode Field-Effect Transistors (FET) is derived and implemented in software. The algorithm is applied to the mask level hardware design of a three micron minimum feature size p well high-speed super buffer. A software representation of the super buffer can be used for the automated design of custom Very-Large-Scale Integrated (VLSI) circuits. Keywords: MacPITTS; Silicon compiler; CMOS; VLSI; Super buffer; Transistor sizing; and High-Speed CMOS.

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Document Details

Document Type
Technical Report
Publication Date
Mar 01, 1988
Accession Number
ADA196526

Entities

People

  • Gordon R. Steele

Organizations

  • Naval Postgraduate School

Tags

DTIC Thesaurus Topics

  • Complementary Metal-Oxide Semiconductors
  • Computer Programs
  • Computers
  • Electrical Engineering
  • Electronic Circuits
  • Electronics
  • Electronics Industry
  • Engineering
  • Field Effect Transistors
  • Integrated Circuits
  • Logic Gates
  • Marine Corps
  • Metal Oxide Semiconductors
  • Metal Oxides
  • Metal-Oxide-Semiconductor Field-Effect Transistors
  • Semiconductor Devices
  • Semiconductors

Fields of Study

  • Engineering

Readers

  • Integrated Circuit Design and Technology.

Technology Areas

  • Microelectronics
  • Microelectronics - Microelectromechanical Systems