An Empirical Study of On-Chip Parallelism
Abstract
This paper presents a methodology for empirically determining the amount of parallelism on a CMOS VLSI chip. Six chips are measured, and the effect of input choice and circuit size is studied. The unexpectedly low parallelism measured here suggests that certain strategies for parallel simulators may be doomed, and earlier efforts to extrapolate parallelism from small circuits to large circuits may have been overly optimistic. Keywords include: On-Chip parallelism, Simulation, Parallel simulation, CMOS VLSI, Spice, RNL, Quarter horse, UNIX.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jun 01, 1988
- Accession Number
- ADA197203
Entities
People
- Lawrence H Snyder
- Mary L. Bailey
Organizations
- University of Washington