Optical Symbolic Processor for Expert System Execution
Abstract
A detailed performance evaluation was begun for our optical architecture, SPARO, for combinator graph reduction. Since the interconnection network was the bottleneck in the performance of the architecture, the focus was on the message throughput of the simple register-based network. An accurate performance model was derived for the equivalent bidirectional ring network and found, both by analysis and simulation, that the net parallelism in the architecture was restricted by the low message traffic in the network. When messages exhibited no locality, the throughput for a 1024 processor network was limited to 8. With local messages, the maximum throughput for the same network was 27. Keywords: Computer architecture; Optical computing; Symbolic programming.
Document Details
- Document Type
- Technical Report
- Publication Date
- May 31, 1988
- Accession Number
- ADA197668
Entities
People
- Aloke Guha
- Julian Bristow
- Subra Natarajan
Organizations
- Honeywell International, Inc.