The Reconfigurable Arithmetic Processor

Abstract

The Reconfigurable Arithmetic Processor (RAP) is an arithmetic processing node for a message-passing, MIMD concurrent computer. It incorporates on one chip several serial, 64 bit floating point arithmetic units connected by a switching network. By sequencing the switch through different patterns, the RAP chip calculates complete arithmetic formulas. By chaining together its arithmetic units the RAP reduces the amount of off chip data transfer; in the examples we have simulated off chip I/O can often be reduced to 30% or 40% of that required by a conventional arithmetic chip. Simulations predict a peak performance of 20M Flops with 800M bit/sec off chip bandwidth in a 2 micron CMOS process.

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Document Details

Document Type
Technical Report
Publication Date
Jun 01, 1988
Accession Number
ADA200784

Entities

People

  • Bill Dally
  • Stuart Fiske

Organizations

  • Massachusetts Institute of Technology

Tags

Communities of Interest

  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Arithmetic
  • Arithmetic Units
  • Artificial Intelligence
  • Bandwidth
  • Computations
  • Computer Architecture
  • Computer Communications
  • Computer Science
  • Computers
  • Computing System Architectures
  • Electrical Engineering
  • Floating Point Operations
  • Pipelines
  • Signal Processing
  • Simulations
  • Switches
  • Template Patterns

Fields of Study

  • Computer science

Readers

  • Approximation Theory.
  • Integrated Circuit Design and Technology.
  • Parallel and Distributed Computing.