Scheme86: An Architecture for Microcoding a Scheme Interpreter

Abstract

This document describes the design and implementation plans for a computer that is optimized as microcoded interpreter for Scheme. The native language of this computer is SCode, a tree-structured, typed-pointer representation of Scheme. The memory system is built with high speed RAM and offers low-latency as well as high throughput. Multiple execution units in the processor complete complex operations in less than one memory cycle to allow efficient use of memory bandwidth. The processor provides hardware support for tagged data objects and runtime type checking. The author will discuss the motivation for such a machine, its architecture why it is expected to interpret Scheme efficiently, and the computer aided design tools I have developed for building this computer.

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Document Details

Document Type
Technical Report
Publication Date
Aug 01, 1988
Accession Number
ADA201258

Entities

People

  • Henry M. Wu

Organizations

  • Massachusetts Institute of Technology

Tags

Communities of Interest

  • Cyber
  • Energy and Power Technologies
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Artificial Intelligence
  • Circuit Boards
  • Computer Architecture
  • Computer Programming
  • Computer Programs
  • Computer Science
  • Computers
  • Computing System Architectures
  • Debugging
  • Electrical Engineering
  • Instruction Set Architecture
  • Language
  • Lisp Programming Language
  • Micro-Machines
  • Printed Circuit Boards
  • Printed Circuits
  • Simulators

Fields of Study

  • Computer science

Readers

  • Computer Science.
  • Parallel and Distributed Computing.