Message-Driven Processor Architecture Version 11

Abstract

The Message Driven Processor is a node of a large-scale multiprocessor being developed by the Concurrent VLSI Architecture Group. It is intended to support fine-grained, message passing, parallel computation. It contains several novel architectural features, such as a low-latency network interface, extensive type-checking hardware, and on-chip memory that can be used as an associative lookup table. This document is a programmer's guide to the MDP. It describes the processor's register architecture, instruction set, and the data types supported by the processor. It also details the MDP's message sending and exception handling facilities. Keywords: Processor architecture, VLSI, Parallel processing, Message driven processor, Fine grain, Networks, Cache, and Concurrent smalltalk.

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Document Details

Document Type
Technical Report
Publication Date
Aug 18, 1988
Accession Number
ADA201618

Entities

People

  • Andrew Chien
  • Bill Dally
  • Brian Totty
  • Jerry Larivee
  • John Keen
  • Peter Nuth
  • Stuart Fiske
  • Waldemar Horwat

Organizations

  • Massachusetts Institute of Technology

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Addressing
  • Arithmetic
  • Artificial Intelligence
  • Assembly Languages
  • Coding
  • Computations
  • Computer Programming
  • Computers
  • Computing System Architectures
  • Instruction Set Architecture
  • Instructions
  • Object Oriented Programming
  • Operating Systems
  • Parallel Computing
  • Parallel Processing
  • Switches
  • Translations

Fields of Study

  • Computer science
  • Engineering

Readers

  • Parallel and Distributed Computing.