Algorithmic Fault Tolerance

Abstract

A reduction in the minimum attainable feature size in integrated circuits has lead to the possibility of more and more complex circuits being built on a single chip (VLSI). This technological advance brings with it the need to make these circuits fault tolerant: to increase yield and reliability and to reduce testing times. This Memorandum briefly reviews current techniques for designing fault tolerant circuits before concentrating on a new, high-level fault tolerance technique: algorithmic fault tolerance. The concept of algorithmic fault tolerance is explained and various techniques are reviewed with regard to their suitability for providing fault tolerance for signal processing algorithms. Suggestions are made for the direction for further research.

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Document Details

Document Type
Technical Report
Publication Date
Sep 01, 1988
Accession Number
ADA202065

Entities

People

  • I. K. Proudler

Organizations

  • Royal Signals and Radar Establishment

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Algebra
  • Algorithms
  • Arithmetic
  • Coding
  • Computer Communications
  • Computer Programming
  • Computer Science
  • Computers
  • Error Correction Codes
  • Fabrication
  • Fault Tolerance
  • Filters
  • Integrated Circuits
  • Mainframe Computers
  • Numbers
  • Signal Processing
  • Two Dimensional

Fields of Study

  • Engineering

Readers

  • Fault Tolerant Diagnosis of Black and White Balloon Isolation Tests Using ¥.
  • Integrated Circuit Design and Technology.
  • Systems Analysis and Design