Calculation of Carriers in Depletion Region of Semiconductors with Capacitance-Voltage Measurements

Abstract

Profiles obtained by the capacitance-voltage (C-V) method cannot give carrier distributions information right from the semiconductor surface. Since the prediction of ultimate device performance depends strongly upon an accurate knowledge of the entire carrier depth profile, it is very important to know this profile for the entire crystal including the surface depletion layer. A method was developed for obtaining the measured C-V data. This method was successfully applied to simulated C-V data created from various known linear, parabolic, and LSS Gaussian distributions, and then finally was demonstrated through experimentally measured C-V profiles obtained from Si-implanted GaAs. In this method, barrier potential was assumed to be 0.8 eV for n-type Si-implanted GaAs. Theses.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1988
Accession Number
ADA202529

Entities

People

  • Jong H. Kim

Organizations

  • Air Force Institute of Technology

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Charge Carriers
  • Charge Density
  • Complementary Metal-Oxide Semiconductors
  • Computer Programs
  • Conduction Bands
  • Electronics Laboratories
  • Energy Bands
  • Energy Levels
  • Fermi Levels
  • Field Effect Transistors
  • Ion Implantation
  • Metal Oxide Semiconductors
  • Modules (Electronics)
  • N Type Semiconductors
  • Schottky Diodes
  • Semiconductor Devices
  • Semiconductors

Fields of Study

  • Materials science

Readers

  • Fluid Dynamics.
  • Semiconductor Device Technology

Technology Areas

  • Microelectronics