Hardware Implementation of a BCH Encoder, Decoder, and Interface

Abstract

A BCH encoder and decoder are implemented in hardware with special emphasis given to the encoder and decoder interfaces. The pitfalls of using a 7474 D flip flop as the basis of building the interface is discussed. The advantages of using a UART for the interface are outlined and the circuit diagrams to implement the UART interface in hardware are provided. Finite impulse response linear filters are chosen to implement both the BCH encoder and decoder. A basic theoretical understanding of the BCH encoder and decoder function is given. Design decisions made for the hardware implementation of the encoder and decoder are discussed, and schematics detailing the final hardware configurations are provided. Software to run and test all of the above is documented in the appendices. Theses.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1988
Accession Number
ADA202807

Entities

People

  • Norman R. Leclair

Organizations

  • Air Force Institute of Technology

Tags

Communities of Interest

  • Human Systems

DTIC Thesaurus Topics

  • Abstracts
  • Air Force
  • Coding
  • Communication Channels
  • Communication Equipment
  • Communication Systems
  • Computer Programming
  • Computers
  • Data Transmission
  • Decoding
  • Detection
  • Digital Communications
  • Electrical Engineering
  • Engineering
  • Simulators
  • Test Beds
  • Transmitters

Fields of Study

  • Engineering

Readers

  • Computational Modeling and Simulation
  • Integrated Circuit Design and Technology.