Fast Design of Good Systolic Systems
Abstract
Advanced high resolution methods for real-time signal processing require fast multi-processor architectures, realized as Very Large Scale Integrated systems, for their implementation. A class of parallel architectures, 'systolic arrays', fulfills the demands of signal processing and at the same time conforms to the limitations of VLSI technology. The design of efficient systems of systolic arrays is an iterative process in which the information gathered from mapping algorithms onto hardware is influential in the development of the algorithms. Presently, the absence of mapping tools makes it extremely difficult to find good systolic implementations for many important problems. Often, one cannot do better than implementing structurally simple but numerically inferior algorithms, which is undesirable for most signal processing tasks. A methodology is proposed that automates the mapping of recurrence equations to processor arrays. Two aspects distinguish our methodology from extant work: (1) complex coupled systems of recurrence equations can be systematically treated and (2) the resulting systolic systems are optimal. The proposed methodology takes as input recurrence equations describing the algorithm, along with certain desirable hardware features. A sophisticated optimization procedures is then applied to generate the description of optimal arrays that implement the algorithm. If there is no satisfactory implementation, the algorithm will have to be revised, in order to improve pipeline-ability, without sacrificing numerical stability.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 12, 1989
- Accession Number
- ADA204773
Entities
People
- Ilse Ipsen
- Jean-marc Delosme
Organizations
- Yale University