Design of Multiple-Valued Programmable Logic Arrays

Abstract

The goal of this thesis is the development of a programmable logic array (PLA) that accepts multiple-valued inputs and produces multiple-valued outputs. The PLA is implemented in CMOS and multiple levels are encoded as current. It is programmed by choosing transistor geometries which control the current level at which the PLA reacts to inputs. An example of a 4-valued PLA is shown. As part of this research, a C program was written that produces a PLA layout.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1988
Accession Number
ADA205307

Entities

People

  • Yong H. Ko

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Advanced Electronics
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Air Force
  • Circuits
  • Computers
  • Data Processing
  • Demographic Cohorts
  • Detection
  • Electrical Engineering
  • Electronics
  • Engineering
  • Fabrication
  • Geometry
  • Information Processing
  • Information Systems
  • Logic Gates
  • Simulations
  • Step Functions
  • Transistors

Readers

  • Computer Programming and Software Development.
  • Integrated Circuit Design and Technology.