Hardware Modeling with VHDL (VHSIC Hardware Description Language) Simulation
Abstract
This thesis presents a study of the VHSIC Hardware Description Language (VHDL) and its ability to accurately model digital hardware circuits. A brief background of Hardware Description Languages and VHDL is presented followed by a detailed look at VHDL's language features and semantics that support hardware modeling. This information is applied to the design and development of a VHDL simulator that supports a subset of the language. A discussion of the simulator design and implementation issues is presented. Theses.
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 01, 1988
- Accession Number
- ADA206356
Entities
People
- Douglas G. Pompilio
Organizations
- Air Force Institute of Technology