A Multiprocessor Architecture Using Modular Arithmetic for Very High Precision Computation
Abstract
This document outlines a multiprocessor architecture that uses modular arithmetic to implement numerical computation with 900 bits of intermediate precision. A proposed prototype, to be implemented with off-the-shelf parts, will perform high-precision arithmetic as fast as some workstations and mini-computers can perform IEEE double-precision arithmetic. The author discusses how the structure of modular arithmetic conveniently maps into a simple, pipelined multiprocessor architecture. He presents techniques developed to overcome a few classical drawbacks of modular arithmetic. This architecture is suitable to and essential for the study of chaotic dynamical systems.
Document Details
- Document Type
- Technical Report
- Publication Date
- Apr 01, 1989
- Accession Number
- ADA208154
Entities
People
- Henry M. Wu
Organizations
- Massachusetts Institute of Technology