A Reconfigurable Arithmetic Processor

Abstract

Achieving high rates of floating-point computation is one of the primary goals of many computer designs. Many high speed floating-point datapaths have been designed in order to address this problem. However, conventional designs often neglect the real problem in achieving high performance floating-point: providing the necessary I/O bandwidth to keep the high speed datapaths busy. The Reconfigurable Arithmetic Processor (RAP) is an arithmetic processing node for a message-passing, MIMD concurrent computer. Its datapath is designed to sustain high rates of floating-point operations, while requiring only a fraction of the I/O bandwidth required by a conventional floating-point datapath. The RAP incorporates on one chip eight 4-bit serial, 64 bit floating-point arithmetic units connected by a switching network. By sequencing the switch through different patterns, the RAP chip calculates complete arithmetic formulas.

Open PDF

Document Details

Document Type
Technical Report
Publication Date
Apr 01, 1989
Accession Number
ADA208323

Entities

People

  • James Alexander
  • Stuart Fiske

Organizations

  • Massachusetts Institute of Technology

Tags

Communities of Interest

  • Energy and Power Technologies
  • Weapons Technologies

DTIC Thesaurus Topics

  • Arithmetic Units
  • Circuits
  • Coding
  • Computations
  • Computer Science
  • Computers
  • Electrical Engineering
  • Engineering
  • Floating Point Operations
  • Lisp Programming Language
  • Plastic Explosives
  • Shift Registers
  • Signal Processing
  • Simulations
  • Simulators
  • Trees (Data Structures)
  • Two Dimensional

Fields of Study

  • Computer science

Readers

  • Parallel and Distributed Computing.