Fault Tolerant VLSI (Very Large-Scale Integration) Design Using Error Correcting Codes

Abstract

Very Large-Scale Integration (VLSI) provides the opportunity to design fault tolerant, self-checking circuits with on-chip, concurrent error correction. This study determines the applicability of a variety of error-detecting, error-correcting codes (EDAC) in high speed digital data processors and buses. In considering both microcircuit faults and bus faults, some of the codes examined are: Berger, repetition, parity, residue, and Modified Reflected Binary codes. The report describes the improvement in fault tolerance obtained as a result of implementing these EDAC schemes and the associated penalties in circuit area.

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Document Details

Document Type
Technical Report
Publication Date
Feb 01, 1989
Accession Number
ADA208337

Entities

People

  • A. M. Ali
  • C. R. Hartmann
  • G. S. Visweswaran
  • P. K. Lala
  • Samiran Ganguly

Organizations

  • Syracuse University

Tags

Communities of Interest

  • Advanced Electronics
  • C4I
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Abstracts
  • Binary Arithmetic
  • Classification
  • Coding
  • Computer Programming
  • Computers
  • Decoding
  • Detectors
  • Diagrams
  • Digital Data
  • Fault Tolerance
  • Information Processing
  • Large Scale Integration
  • Notation
  • Security
  • Symbols
  • Very Large Scale Integration

Fields of Study

  • Engineering

Readers

  • Applied Combinatorial Optimization and Logic Circuit Design.
  • Computer Programming and Software Development.
  • Integrated Circuit Design and Technology.

Technology Areas

  • Microelectronics
  • Microelectronics - Microelectromechanical Systems