Easily Testable PLA-Based Finite State Machines
Abstract
This paper outlines a synthesis procedure, which beginning from a State Transition Graph description of a sequential machine, produces an optimized easily testable PLA-based logic implementation. Previous approaches to synthesizing easily testable sequential machines have concentrated on the stuck- at fault mode. For PLAs, and extended fault model called the crosspoint fault model is used. This paper, proposes a procedure of constrained state assignment and logic optimization which guarantees testability for all combinationally irredundant crosspoint faults in a PLA-based finite state machine. No direct access to the flip-flops is required. The test sequences to detect these faults can be obtained using combinational test generation techniques alone. This procedure thus represents an alternative to a Scan Design methodology. We present results which illustrate the efficacy of this procedure--the area/ performance penalties in return for easy testability are small.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 01, 1989
- Accession Number
- ADA208371
Entities
People
- A. R. Newton
- Hi-keung T. Ma
- Srinivas Devadas
Organizations
- Massachusetts Institute of Technology