Shared Memory versus Message Passing Architectures: An Application Based Study
Abstract
The diminishing differences between the hardware structure of shared memory and message passing parallel computers mandate a new evaluation of the tradeoffs these architectures impose on the development and performance of applications. In a message passing computer, some message traffic is used to perform interprocessor updates which maintain consistency between the various processors data. Consider this traffic to be analogous to global bus traffic needed in shared memory computer for hardware cache consistency. Using Locus- Route, a global router for standard cell, as a case study, we investigate the level of traffic required to maintain consistency of data with each of the two architectures. By explicitly varying the frequency of interprocessor updates, the level of traffic in the message passing approach can be reduced to as little as 1% of the traffic in the shared memory approach while still obtaining solution quality within 10% of the quality given by the shared memory version. We show that exploiting locality, in the way wires to be routed are assigned to processors, can further lower this message traffic yb as much as 67%. However, the degree to which locality can be exploited may be limited by the opposing requirement that the application be load balanced, as well as by limited locality in the data set. Keywords: Computer architecture.
Document Details
- Document Type
- Technical Report
- Publication Date
- Nov 09, 1988
- Accession Number
- ADA210312
Entities
People
- Anoop Gupta
- Margaret Martonosi
Organizations
- Stanford University