Final Evaluation of MIPS M/500
Abstract
In response to a request from the DoD, an analysis of a Reduced Instruction Set Computer (RISC) processor, the MIPS M/500, was performed. All aspects of processor capabilities and support software were evaluated, tested, and compared to familiar Complex Instruction Set Computer (CISC) architectures. In all cases, the RISC computer and its support software performed better than a comparable CISC computer. This report provides the general and specific results of these analyses, along with the recommendation that the DoD and other government agencies seriously consider this or other RISC architectures as a highly viable and attractive alternative to the more familiar but less efficient CISC architectures.
Document Details
- Document Type
- Technical Report
- Publication Date
- Nov 01, 1987
- Accession Number
- ADA210316
Entities
People
- Daniel V. Klein
- Robert Firth
Organizations
- Carnegie Mellon University