The Organization of Permutation Architectures with Bussed Interconnections
Abstract
This paper explores the problem of efficiently permuting data stored in VLSI chips in accordance with a predetermined set of permutations. By connecting chips with shared bus interconnections, as opposed to point-to-point interconnections, we show the number of pins per chip can often be reduced. We also consider uniform permutation architectures that realize permutations in several clock ticks, instead of one, and show that further savings in the number of pins per chip can be obtained. Keywords: Barrel shifter, Bussed interconnections, Cyclic shifter, Difference cover, Difference set, Group theory, Permutation, Permutation architecture, Projective plane, Special-purpose architecture, Uniform architecture.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 01, 1989
- Accession Number
- ADA210832
Entities
People
- Charles E. Leiserson
- Joe Kilian
- Sholomo Kipnis
Organizations
- Massachusetts Institute of Technology