A Single-Phase Clocked NOR/NOR CMOS Programmable Sequential Array Structure

Abstract

A static CMOS Programmable Sequential Array (PSA) structure is presented, which uses a precharge CMOS NOR/NOR logic structure to implement combinational logic. It is fast, it consumes no static power, and it imposes no limits on the number of input terms. Only one input clock is required while additional clocks are generated by the PSA structure. Static latches are added to the output. Results will remain unchanged with the absence of a high clock signal. This single-phase clocking technique, with statistically latched outputs, permits this proposed PSA to be used for many different system overall timing strategies. The proposed methodology has been implemented with MOSIS scalable design rules and has been adapted into the Berkeley VLSI CAD tool system--MPLA's tiling format. An automatically generated example is given.

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Document Details

Document Type
Technical Report
Publication Date
Apr 01, 1989
Accession Number
ADA211297

Entities

People

  • Shih-lien Lu

Organizations

  • University of Southern California

Tags

Communities of Interest

  • Advanced Electronics
  • Air Platforms

DTIC Thesaurus Topics

  • Abstracts
  • California
  • Circuits
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  • Complementary Metal-Oxide Semiconductors
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  • Diagrams
  • Diffusion
  • Information Science
  • Integrated Circuits
  • Logic
  • Nand Gates
  • Procurement
  • Schematic Diagrams
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  • Trailing Edges
  • Transistors

Fields of Study

  • Physics

Readers

  • Integrated Circuit Design and Technology.