Redundancies and Don't Cares in Sequential Logic Synthesis
Abstract
The relationships between redundant logic and don't care conditions in combinational circuits are well known. Redundancies in a combinational circuit can be explicitly identified using test generation algorithms or implicitly eliminated by specifying don't cares for each gate in the combinational network and minimizing the gates, subject to the don't care conditions. In this paper, we explore the relationships between redundant logic and don't care conditions in sequential circuits. Stuck-at faults in a sequential circuit may be testable in the combinational sense, but may be redundant because they do not alter the terminal behavior of anon-scan sequential machine. The sequential redundancies result in a faulty State Transition Graph (STG) that is equivalent to the STG of the true machine. We present a classification of redundant faults in sequential circuits composed of single or interacting finite state machines.
Document Details
- Document Type
- Technical Report
- Publication Date
- May 01, 1989
- Accession Number
- ADA211931
Entities
People
- A. R. Newton
- Hi-keung T. Ma
- Srinivas Devadas
Organizations
- Massachusetts Institute of Technology