An Accurate Timing Model for Fault Simulation in MOS Circuits
Abstract
With the increasing need for manufacturers to maintain quality requirements for high performance and high density MOS VLSI integrated circuits and the multitude of physical failures and defects that can occur in such circuits, delay fault testing is gaining importance. An extremely important component of such a delay test generation environment is an accurate yet fast delay fault simulator. The goal of fault simulation is to generate the responses of digital circuits under both fault and fault-free conditions, without prohibitive cost. Most simulators available today either sacrifice accuracy or are very time-consuming. Therefore, choosing the right simulation model is the key in fault simulation. MOS circuit models that were previously developed for true value simulation, after being modified to accommodate fault models, have been used by fault simulators, such as FMOSSIM. These fault simulators are incapable of detecting timing errors and even some logic errors, both of which occur in actual failures in the MOS circuits. Others have shown that some faults only affect the circuit timing and the delay may invalidate test sets. Therefore, fault simulators must consider the circuit delay in order to evaluate test sets accurately. FAUST is one such fault simulator which very accurately detects timing as well as logical errors. It was based on using a combination of table lookup and numerical integration techniques to solve differential equations.
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 01, 1989
- Accession Number
- ADA213153
Entities
People
- Sungho Kim
Organizations
- University of Illinois Urbana–Champaign