Technology Development and Circuit Design for a Parallel Laser Programmable Floating Point Application Specific Processor
Abstract
The laser programmable floating point application specific processor (LPASP) is a new approach at rapid development of custom VLSI chips. The LPASP is a generic application specific processor that can be programmed to perform a specific function. The effort of this thesis is to develop and test the double precision floating point adder and the laser programmable read-only memory (LPROM) that are macrocells within the LPASP. In addition, the thesis analyzes the applicability of an LPASP parallel processing system. The double precision floating point adder is an adder/subtractor macrocell designed to comply with the IEEE double precision floating point standard. An 84-pin chip of the adder was fabricated using 2 micron feature sizes. The fastest processing time was measured at 120 nanoseconds over 23 worst case test vectors. The adder uses the optimized carry multiplexed (OCM) adder that was developed at AFIT. The OCM adder is a new adder architecture that uses four parallel carry paths to attain a performance time on the order of (cubed root of M) with a gate count on the order of O (n). The redundant logic associated with the parallel propagation banks is eliminated in the OCM adder so that the largest bit-slice of the adder contains only eight 2-to-1 multiplexer gates. A 57-bit adder was fabricated using 2 micron feature sizes. The processing time for the adder is 31 nsec. Theses. (rrh)
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 01, 1989
- Accession Number
- ADA215870
Entities
People
- Michael W. Scriber
Organizations
- Air Force Institute of Technology