A Scalable Multiprocessor Architecture Using Cartesian Network - Relative Addressing
Abstract
The Computer Architecture Group is developing a new model of computation called L. This thesis describes a highly scalable architecture for implementing L called CNRA. In the CNRA architecture, processor/memory pairs are placed at the nodes of a low-dimensional Cartesian grid network. Addresses in the system are composed of a routing component which describes a relative path through the interconnection network (the origin of the path is the node on which the address resides), and a 'memory location' component which specifies the memory location to be addressed on the node at the destination of the routing path. The CNRA addressing system allows sharing of data structures in a style similar to that of global shared memory machines, but does not have the disadvantages normally associated with shared-memory machines (i.e. limited address space and memory access latency that increases with system size). This thesis discusses how a practical CNRA system might be built. It discusses how the system software might manage the 'relative pointers' in a clean, transparent way, solutions to the problem of testing pointer equivalence, protocols and algorithms for migrating objects to maximize concurrency and communication locality, garbage collection techniques, and other aspects of the CNRA system design. Simulations experiments with a toy program are presented. Multiprocessors; Scalability; Topology; Address space; Relative addressing; Task migration; Parallelism.
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 01, 1989
- Accession Number
- ADA216580
Entities
People
- Joseph D. Morrison
Organizations
- Massachusetts Institute of Technology