Modeling A Circuit Switched Multiprocessor Interconnect
Abstract
This study began as an attempt to understand discrepancies between Patel's classic model of a circuit-switched interconnection network and simulations as part of the MIT ALEWIFE Multiprocessor project. After a careful analysis of Patel's model, we developed a model with fewer approximations that produced results generally closer to detailed simulation. The major source of inaccuracy in patel's model is the unit-request approximation, which treats a t- cycle request as t l-cycle requests producing significant inaccuracies for networks with many switching levels and for small packet sizes. Our model followed the behavior of the network more closely, explicitly modeling the effects of switch size, network depth, packet size and memory latency, thereby alleviating some inaccuracies in Patel's model. However, despite the slightly lower accuracy of Patel's model, we believe that its simplicity makes it the practical choice for most applications. Thus, our main contribution was to understand the causes of inaccuracies in both models, allowing us to predict the quality of the estimations they yielded. Another research result is validating a complicated simulator using relatively simple models, not a common use for a model. We found that some of the original discrepancies between patel's model and the simulator were due to hidden inconsistancies between parameters used by the model and those used by the simulator, and that others were duet to bugs in the simulator code.
Document Details
- Document Type
- Technical Report
- Publication Date
- Oct 01, 1989
- Accession Number
- ADA217122
Entities
People
- Anant Agarwal
- Daniel Nussbaum
- Ingmar Vuong-adlerberg
Organizations
- Massachusetts Institute of Technology