Radiation-Hardened Wafer Scale Integration
Abstract
This report describes the logical and physical design of a prototype focal plane processor to be built as a wafer-scale circuit in a radiation-hard CMOS process. Design details and test results are presented for the five circuits which were fabricated in bulk CMOS through the MOSIS fabrication service. The floor plan of the wafer is described. This project was terminated before the wafer-scale circuit could be fabricated. New methods and equipment for fabrication of SOI wafers by zone-melting-recrystallization are described, as well as experience in fabricating CMOS circuits on these wafers. A summary is given of results in related work on fabrication of rad-hard gate dielectrics.
Document Details
- Document Type
- Technical Report
- Publication Date
- Oct 25, 1989
- Accession Number
- ADA217332
Entities
People
- Allan H. Anderson
- Bor-yeu Tsaur
- C. E. Woodward
- Chenson K. Chen
- Gregory J. Dunn
- James A. Burns
- Kenneth H. Konkle
- P. W. Wyatt
Organizations
- Massachusetts Institute of Technology