Asynchronous Design for Parallel Processing Architectures

Abstract

The objective of this research is to provide an interconnect design synthesis methodology which facilitates a modular design approach without compromising the global performance. The main tasks of this effort will be the development of the theory for optimal interconnect synthesis from a high-level specification, with emphasis on testability and fault-tolerance asynchronous interface among parallel computing hardware objects, and the application of this design methodology to physical implementations of multi-processing systems.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1989
Accession Number
ADA217421

Entities

People

  • Teresa H. Meng

Organizations

  • Stanford University

Tags

Communities of Interest

  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Algorithms
  • Boolean Algebra
  • Circuit Interconnections
  • Communication Systems
  • Detectors
  • Electronic Mail
  • Fault Tolerance
  • Graph Theory
  • Parallel Computing
  • Parallel Processing
  • Petri Nets
  • Phase
  • Phase Detectors
  • Robotics
  • Specifications
  • Standards

Fields of Study

  • Computer science

Readers

  • Parallel and Distributed Computing.
  • Software Engineering