ISITE: Automatic Circuit Synthesis for Double-Metal CMOS VLSI (Very Large Scale Integrated) Circuits

Abstract

Very large scale integrated (VLSI) circuit technology allows one to manufacture chips with several million devices. Designing such large circuits cannot be accomplished without design automation tools and computer-aided design tools. This thesis addresses the problem of automatic circuit synthesis for double-metal Complementary Metal Oxide Semiconductors technology. Large circuits are partitioned into cells and represented as incidence matrices. The rows and columns of these matrices are folded to minimize the area. A symbolic layout is then generated for each matrix. This symbolic layout is then used to generate the physical mask layers necessary for fabrication in the metal-metal matrix methodology. Keywords: Theses.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1989
Accession Number
ADA217459

Entities

People

  • Perry Gee

Organizations

  • University of Illinois Urbana–Champaign

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Complementary Metal-Oxide Semiconductors
  • Computer Programming
  • Computer Programs
  • Computer-Aided Design
  • Computers
  • Detection
  • Engineers
  • Fabrication
  • Integrated Circuits
  • Language
  • Logic
  • Logic Devices
  • Logic Gates
  • Packing Density
  • Semiconductors
  • Standards
  • Two Dimensional

Fields of Study

  • Engineering

Readers

  • Computer Programming and Software Development.
  • Semiconductor Device Technology
  • Software Engineering.

Technology Areas

  • Microelectronics