VHSIC Hardware Description Language (VHDL) Benchmark Suite

Abstract

This report documents the development of a VHDL Benchmark Suite system. Each benchmark is designed to test one or more of a set of 71 VHDL language features in terms of the limitations of user's of vendor's system architecture, operating system, and VHDL toolset. These limitations could include CPU time and amount of memory required to analyze, model generate, build and simulate a test. Examples of language feature tests are the maximum number of signal declarations allowed in an architecture or the number of input ports allowed in the port clause of a component before errors are caused. Keywords: Computer programming, VHDL - IEEE 1076 - Design language-hardware description, Computer hardware.

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Document Details

Document Type
Technical Report
Publication Date
Oct 01, 1989
Accession Number
ADA217947

Entities

People

  • Karen Serafino

Organizations

  • Wright Laboratory

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  • Materials and Manufacturing Processes

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Fields of Study

  • Computer science
  • Engineering

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  • Database Systems and Applications
  • Integrated Circuit Design and Technology.