Experimental High Speed/Power Ratio ASIC Designs Using Residue Numbers
Abstract
Residue numbers have traditionally been popular for signal processing applications and have recently received renewed interest, for a number of reasons. The inherent parallelism of the residue number system enables the throughput of a system to be increased while keeping the cost reasonable. With the advent of VLSI circuits, the increased size and complexity of parallel residue number circuits may no longer be prohibitive. A method for implementing onboard signal processing algorithms using CMOS Application Specific Integrated Circuits (ASIC) is presented in this report. This method uses residue arithmetic in a one-out-of-n representation. The representation and implementation methods provide low-power circuits that retain their high-performance capabilities. Details of the adder and multiplier circuits are given, along with an overview of the input/output conversion logic. A specific example algorithm that performs a matrix multiplication has been chosen and implemented. Test chips of the adder demonstrate that the add function performs within our design constraints. Test chips of the algorithm for a particular residue have demonstrated that the arithmetic portions of the chip functioned as expected. Some preliminary results are included at the end of this report with some caveats regarding the particular implementation that we choose.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 15, 1990
- Accession Number
- ADA220302
Entities
People
- A. Parker
- A. Simoneau
- J. Pizarro
Organizations
- The Aerospace Corporation