Balance in Architectural Design

Abstract

We introduce a performance metric, normalized time, which is closely related to such measures as the area-time product of very large scale integration theory, and the price/performance ratio of advertising literature. This metric captures the idea of a piece of hardware pulling its own weight, i. e. contributing as much to performance as it costs in resources. We then prove general theorems for stating when the size of a given part is in balance with its utilization, and give specific formulas for commonly found linear and quadratic devices. We also apply these formulas to an analysis of a specific processor element, and discuss the implications for bit-serial vs word-parallel, RISC vs CISC, and VLIW designs.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1989
Accession Number
ADA220835

Entities

People

  • Larry Snyder
  • Samuel Ho

Organizations

  • University of Washington

Tags

Communities of Interest

  • Cyber

DTIC Thesaurus Topics

  • Case Studies
  • Computations
  • Computer Components
  • Computers
  • Computing System Architectures
  • Decoding
  • Engineering
  • Equations
  • Instruction Set Architecture
  • Instructions
  • Models
  • Parallel Computing
  • Parallel Processors
  • Serial Processors
  • Software Prototyping
  • Theses
  • Very Large Scale Integration

Fields of Study

  • Mathematics

Readers

  • Calculus or Mathematical Analysis
  • Parallel and Distributed Computing.