Timing Optimization of Multi-Phase Sequential Logic
Abstract
High-performance MOS circuits are frequently designed using pre- charged and dynamic logic. This requires the use of multiple phases of the system clock to ensure that the circuitry is pre-charged and refreshed at the proper times during each clock cycle. Finite-state machines used to control this type of logic must therefore be constructed as multi-phase sequential logic with inputs and outputs stable during the appropriate phases. The timing optimization of multi-phase logic entails the reduction of the overall cycle time of the machine as well as input to output delays by distributing computation throughout the entire clock cycle. Currently, no tools are available to automatically perform this optimization task for multi-phase logic. We have developed such a tool as a set of extensions to the combinational logic optimization tool, misII. Our algorithms yield improvements that are 20% better than what is achievable using only combinational logic optimization tools that do not move logic across latches. Furthermore, we achieve 65% of the improvements possible in the circuits show average input to output delay improvements of almost 20% with area penalties of less than 12%. For a four-phase controller used in the SPUR processor it yields an improvement in cycle time of 21% with an area penalty of 21%.
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 01, 1989
- Accession Number
- ADA220836
Entities
People
- Gaetano Borriello
- Karen Bartlett
- Sitaram Raju
Organizations
- University of Washington