Implementation of an I-Structure Memory Controller
Abstract
Memory systems in large-scale parallel processors are characterized by high bandwidth requirements, and long access latency. Because many processors are issuing concurrent memory requests, requests can arrive at the memory in any order. Dataflow processors present an elegant and clean solution for synchronizing parallel tasks and tolerating long memory latency by providing hardware synchronization for individual instructions, single word task- continuations, and split-phase memory transactions. These same ideas are applied to the development of a high-bandwidth memory system with hardware support for synchronization. Synchronization does not cause busy-waiting or retrying; synchronization delays appear to the processors simply as long latency memory accesses. I-structures are a method of memory access developed as an extension to the functional language Id to provide efficient data structures. Functional languages have the very important property of determinacy; program results are independent of the execution order of parallel tasks. By restricting each location to be write-once, data structures can remain determinate, regardless of the order of requests. The hardware stores, as lists, read request of unwritten locations. These deferred requests are serviced automatically when the value is written. Different methods for storing lists of deferred requests are investigated. Keywords: Monsoon processor.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 01, 1990
- Accession Number
- ADA221397
Entities
People
- Kenneth M. Steele
Organizations
- Massachusetts Institute of Technology