A 4-Kbit Four-Transistor Dynamic Ram

Abstract

The design of a 64-word by 64-bit dynamic RAM is described. The RAM cell is implemented as a four-transistor dynamic cell. Sense amplifiers are used to reduce access time. Bootstrapped logic reduces power dissipation. Experimental results indicate a typical cycle time of 160ns and power dissipation of 160nW.

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Document Details

Document Type
Technical Report
Publication Date
Jun 23, 1983
Accession Number
ADA221477

Entities

People

  • Hank Walker

Organizations

  • Carnegie Mellon University

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Amplifiers
  • Circuits
  • Clocks
  • Computer Programming
  • Computer Science
  • Computers
  • Data Acquisition
  • Delay Lines
  • Dissipation
  • Generators
  • High Voltage
  • Lessons Learned
  • Logic
  • Low Voltage
  • Shift Registers
  • Simulators
  • Voltage

Fields of Study

  • Physics

Readers

  • Integrated Circuit Design and Technology.
  • Parallel and Distributed Computing.