CHI-5 Array Processor Support
Abstract
The CHI-5, a low-cost, generalized array processor, was developed under an earlier DARPA contract, MDA903-78-C-0313 as part of an effort to develop low-cost packet speech hardware. The CHI-5 was used successfully by CHI Systems, Inc. and SRI International for digital voice coding using linear predictive coding (LPC) for transmission through packet-switched networks. In support of the DARPA program in packetized speech, the CHI-5 could be used not only for the basic LPC algorithms, but also to support development and demonstration of algorithms for degraded speech environments, and integration of voice and data transmissions. In addition, the CHI-5 could serve as a low-cost compute server, attached to a host computer, to support circuit simulation in programs developing other low-cost speech hardware. This report describes the hardware and software which was developed during this contract. Section 1 is a description of the hardware enhancements of the CHI-5 and the construction of the additional ten units. Section 2 describes the program development software, including a micro-code assembler and linker, a micro-instruction simulator, and a macro-language assembler and linker. Section 3 describes the interface program to support control and data transfer protocols for use of the serial interface for digital voice, data and control transfers. The appendix contains the micro- code developed for the system and a listing of the serial interface control program.
Document Details
- Document Type
- Technical Report
- Publication Date
- Apr 01, 1985
- Accession Number
- ADA221570
Entities
People
- Glen J. Culler
- Jean A. Nisbet
- Judith B. Bruckner
- Michael Mccammon
- Thomas W. Fuller
- Virginia R. Grant
Organizations
- CHI Systems (United States)