Efficient Instruction Sequencing with Inline Target Insertion
Abstract
The trend of deep pipelining and multiple instruction issue has made instruction sequencing an extremely critical issue. Traditionally, compiler- assisted instruction sequencing methods have been considered not suitable for deep pipelining and multiple instruction issue. Hardware methods such as Branch Target Buffers have been proposed for deep pipelining and multiple instruction issue. This paper defines Inline Target Insertion, a specific compiler and pipeline implementation method for Delayed Branches with Squashing. The compiler part of Inline Target Insertion has been shown to be straightforward with an implementation in the IMPACT-I C Compiler. A new code expansion control method has been proposed and included in the implementation. The code expansion and instruction sequencing efficiency are measured for real UNIX and CAD programs. The size of programs, the variety of programs, and the variety of inputs to each program are significantly larger than those used in the previous experiments. The stability of code restructuring based on profile information is proved empirically using a large number of diverse inputs to each benchmark program. The results show that Inline Target Insertion achieves high sequencing efficiency at a small cost of code expansion for deep pipelining and multiple instruction issue.
Document Details
- Document Type
- Technical Report
- Publication Date
- May 01, 1990
- Accession Number
- ADA222807
Entities
People
- Pohua P. Chang
- Wen-mei Hwu
Organizations
- University of Illinois Urbana–Champaign