Gallium Arsenide Pilot Line for High Performance Components
Abstract
The Gallium Arsenide Pilot Line for High Performance Components (Pilot Line III) is to develop a facility for the fabrication of GaAs logic and memory chips. We have completed the first thirty-six months of this contract, and this report covers the period from September 25, 1989, through March 25, 1990. All the elements of this program are now in place. HCAD, our 'User Friendly' CAD system, is complete; it was used to design two successful circuits- the Standard Cell Transversal Filter Chip (TFC) and the Cell Array Casino Test Chip. Our work with 200 MHz, stepping-stone PT-2M memory is complete. The first wafers of 4K SRAM have recently been fabricated, and we have a design trick planned to enhanced the 125C operation of the second iteration of the 4K SRAM. The Custom ALU, Standard Cell TFC, Standard Cell ALU, and 1K Cell Array logic circuits all show similar performance. They satisfy the power supply, speed, and temperature design goals, but they don't comply with the I/O voltage requirements. (JES)
Document Details
- Document Type
- Technical Report
- Publication Date
- Jun 11, 1990
- Accession Number
- ADA223261
Entities
People
- E. F. Lapham
- Robert C. Vehse