A High-Speed KDL-RAM File System for Parallel Computers
Abstract
Here we present the design, implementation, and performance of a main memory file system. The implementation is based on a two-stage abstract parallel processing model whose objective is to maximize throughput and minimize response time. To maximize throughput, lock structures, access structures, and shared variables are distributed among the shared memories. A new, hash-based approach for parallel accesses is used. The effect of lock conflicts are minimized by an optimistic locking protocol. Analytical models are developed for hot-spot memory, distributed-data accesses, and space-vs-time trade-offs for fast accesses to records. Based on the performance results of these models, a high- speed KDL-RAM File System has been implemented on the Butterfly PLUS Parallel Processor and its performance results are given. We show that the performance improvement of this system is considerably better than Bolt, Beranek, and Newman, Inc.'s (BBN's) Butterfly RAMFile System on the Butterfly Parallel Processor. (kr)
Document Details
- Document Type
- Technical Report
- Publication Date
- Jun 22, 1990
- Accession Number
- ADA223299
Entities
People
- C. Severance
- S. Pramanik
- T. J. Rosenau
Organizations
- United States Naval Research Laboratory