Touchstone Project: Milestone Event Q4
Abstract
The focus of this quarter's technical activities has been demonstrating the DELTA numeric node and porting Mach to the IOTA I/O node. In addition, we determined our MRC strategy for the DELTA prototype, completed development of the GAMMA prototype, and finalized our DELTA system architecture. Based on the i860 microprocessor, the DELTA numeric node offers preliminary 40 MHz performance of 8.76 double-precision MFLOP's on the 100 x 100 LINPACK test. The Mach port was successful but requires future work in the network message server and in improving message-passing performance. For the DELTA prototype, we will use the Caltech MRC in the standard MOSIS package but limit its channel bandwidth to 40 MB/s. Our GAMMA prototype proved highly successful and features up to 128 compute nodes and peak performance of 7.6 double precision GFLOP's. Finally, our expectations for the DELTA prototype are equally impressive as it will scale to 512 nodes in a mesh interconnection network and provide 30.7 peak double precision GFLOP's, up to 32 GBytes of distributed memory, and over 150 GBytes of off-line disk storage. (kr)
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 28, 1989
- Accession Number
- ADA224034
Entities
People
- Sig Lillevik
Organizations
- Intel Corporation