A VHDL Interface for Altera Design Files
Abstract
Altera Erasable Programmable Logic Devices (EPLDs) are chips that can be custom designed. These EPLDs are individually described by their Altera Design Files (ADFs). The language structure of ADFs is not directly supported by the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL). VHDL is a software language that was selected as the IEEE standard for a hardware description language. This thesis describes a program that is capable of transforming an ADF into a VHDL entity declaration and entity structural architecture. The scope of ADFs the program transforms is limited to ADFs that contained only Altera primitives and are not of the State Machine Format. The transformation program was developed on a Personal Computer (PC) and the programming language used was Turbo C by Borland. (rh)
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 01, 1990
- Accession Number
- ADA224476
Entities
People
- Jerome P. Nutter
Organizations
- Air Force Institute of Technology