Basic Properties and Limits of Integrated Arrays of Dissipative Circuit and Logic Elements

Abstract

The efforts are divided into the following categories: (a) the effect of scaling on the performance of integrated device arrays; (b) the development of pipelined content addressable memory; (c) the development of integratable fuzzy neurons; (d) the mapping of graph searches into systolic arrays; and (e) the study of ferroelectric capacitors for application in novel integrated circuits. (rh)

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Document Details

Document Type
Technical Report
Publication Date
Jan 01, 1989
Accession Number
ADA224533

Entities

People

  • Robert O. Grondin

Organizations

  • Arizona State University

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Algorithms
  • Artificial Intelligence
  • Automata
  • Circuit Analysis
  • Circuits
  • Computations
  • Computers
  • Content Addressable Memory
  • Electrical Engineering
  • Engineering
  • Formal Languages
  • Information Processing
  • Information Systems
  • Integrated Circuits
  • Language
  • Neural Networks
  • Two Dimensional

Fields of Study

  • Engineering

Readers

  • Business Analytics
  • Integrated Circuit Design and Technology.