Guidance, Navigation and Control. Digital Emulation Technology Laboratory. Volume 5. Task 4, 5, and 7: Software Development and GN&C Processor Development
Abstract
A set of VLSI chips is being designed for the guidance, navigation, and control (GN&C) of KEW interceptors. The GN&C processor consists of three types of architectures: executive processor (EP), data processor (DP), and signal processor (SP). The EP is a general purpose processor with extensive general processing, numerical, and I/O capabilities. The DP is a numerical processor that is specifically designed to solve ordinary differential equations associated with closed-loop control systems. The SP is designed to process image data from a high resolution focal plane array. These processings include several filtering stages, an object clustering stage, and an object centroiding stage. Two VLSI chips are associated with the EP design. They are in the design stage. All the VLSI chips associated with the DP have been fabricated and tested. A prototype multiwire DP module has also been built and tested. Six VLSI chips are associated with the SP design. Three are in the design stage. Three are currently being fabricated. The integrated parallel programming framework (IPPF) is a parallel programming environment for the development of parallel software applications targetted for the GN&C processor and the real-time simulation testbed (Parallel Function Processor). The environment features a graphical programming front-end interface that allows system programmers to construct application and system software based on block diagram programming approach. Most work is concentrated on the low level utilities that are necessary to construct the integrated framework. The front-end graphical interface is still in its early stages of development. (jhd)
Document Details
- Document Type
- Technical Report
- Publication Date
- Jul 22, 1990
- Accession Number
- ADA225127
Entities
People
- Karsten Schwan
- W. S. Tan
Organizations
- Georgia Tech