EPLD Modeling with VHDL

Abstract

Incompatibility between separately-designed subsystems has long been a problem in the logic design industry. This problem greatly affects the productivity of logic design procedures. It also makes system maintenance and second source procurement very difficult. The military and IEEE 1076 standard hardware description language VHDL is a promising solution to this problem. In this thesis, the VHDL language was used to model an industry-wide popular device -- erasable programable logic device (EPLD). The EPLD modeling problems are discussed via the modeling of two EPLD chips, EP310 and EP1800. The solutions of these problems are described and tested. The goal of this thesis is to provide examples of VHDL coding techniques related to the EPLD modeling. These coding techniques with the associated EPLD library can be used to support future system level logic design. Theses.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1989
Accession Number
ADA225434

Entities

People

  • Shih-ming Shu

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Ground and Sea Platforms
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Circuits
  • Computer Programming
  • Computer Programs
  • Computer-Aided Design
  • Computers
  • Electrical Engineering
  • Engineering
  • Information Transfer
  • Integrated Circuits
  • Language
  • Logic
  • Logic Devices
  • Logic Gates
  • Procurement
  • Simulations
  • Simulators
  • Standards

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  • Marine Mammal Biology