Timing Margin Measurement Using a Laser Technique

Abstract

This report describes a non-contact techniques for obtaining information about the timing margins of internal signal paths in CMOS circuits. A controlled photocurrent is injected by spot illumination of an OFF transistor drain loading a node. The collected photocurrent aids or opposes transistors driving the node. This increases (or decreases) node switching times, and many manifest as a change in the maximum operating frequency of the overall circuit. An approach for extracting timing margin values from plots of maximum operating frequency vs illumination intensity has been developed, which does not require estimation of the drive strength or capacitive load of the node tested. Theory, implementation details, difficulties, and test results on a CMOS microprocessor are discussed.

Open PDF

Document Details

Document Type
Technical Report
Publication Date
Jul 01, 1990
Accession Number
ADA226821

Entities

People

  • Glenn C. Fuller
  • Harold K. Brown
  • Shane S. Clammae

Organizations

  • University of Central Florida

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Charge Carriers
  • Failure Mode And Effect Analysis
  • Geometry
  • Information Processing
  • Integrated Circuits
  • Logic Gates
  • Measurement
  • Modules (Electronics)
  • Optics
  • Power Electronics
  • Semiconductor Devices
  • Semiconductors
  • Test And Evaluation
  • Test Beds
  • Test Equipment
  • Test Fixtures
  • Test Methods

Readers

  • Image Processing and Computer Vision.
  • Integrated Circuit Design and Technology.
  • Mathematics or Statistics

Technology Areas

  • Directed Energy