A Pipelined Implementation of Notch Filters Using Genesil Silicon Compiler

Abstract

To implement an IIR notch filter is theoretically feasible but not technically verified or validated. Two methods often used to speed up a computation are multiprocessing and pipelining. In designing a notch filter the pipelining technique is the natural choice to speed up its processing speed. To have a rapid prototype design we may employ the silicon compiler techniques and explore numerous design variations before sending for fabrication. This paper will report the alternative pipelined design of IIR notch filters. We will present the problem, explain the methodologies used in our investigation, analyze the results, and discuss the findings. We first summarize various fixed- point designs for the pipeline building component, the multiplier-adder pair. We then present the design considerations about the system integration. Various parameters are investigated in our research: pipelined stages, timing, silicon area. Additionally, the experiences and difficulties of using timing verifiers that are built in the silicon compiler will be discussed as well.

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Document Details

Document Type
Technical Report
Publication Date
Mar 01, 1990
Accession Number
ADA227605

Entities

People

  • Chih-fu Kung

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Analog Signals
  • Application-Specific Integrated Circuits
  • Bandstop Filters
  • Circuits
  • Coefficients
  • Communication Systems
  • Computers
  • Digital Filters
  • Engineering
  • Fabrication
  • Filters
  • Frequency
  • Notch Filters
  • Pipelines
  • Schools
  • Standards
  • United States Naval Academy

Fields of Study

  • Engineering

Readers

  • Integrated Circuit Design and Technology.
  • Phased Array Antenna Design.
  • Systems Analysis and Design