Macrostructure Logic Arrays. Volume 3. Task 3: Parallel Function Processor Technology
Abstract
The DETL (Digital Emulation Technology Laboratory) simulation hardware centers on the development, implementation, and use of the Parallel Function Processor (PFP). The PFP is a 64 processor digital computer for use in computationally intensive applications that can be partitioned into functional blocks. The processors are grouped in two 32 processor clusters running from one common host. Each 32 processor cluster is connected by a crossbar switch. All inter-processor communication takes place over the crossbar(s). Simultaneous transfers may take place independently and switch patterns may be changed every cycle. In order to program the machine correctly, all inter-processor communication and data transfer lengths must be known beforehand. The PFP has been designed to accommodate 'hardware in the loop' simulations running in real time. Actual hardware components may first be simulated on one or more processors and later replaced with actual hardware interfaced to specified crossbar ports. The inputs and outputs to/from the device will appear identical to those it would see in an actual system. (kr)
Document Details
- Document Type
- Technical Report
- Publication Date
- Nov 07, 1990
- Accession Number
- ADA228564
Entities
People
- Cecil O. Alford
- David Palusky
- Michael B. Woods
- Philip R. Bingham
- Richard M. Pitts
Organizations
- Georgia Tech